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High Bandwidth Memory (HBM3) Products | SK Hynix | Samsung | Nvidia and related IEEE Papers

High Bandwidth Memory (HBM3)

JEDEC has released HBM3 with the JESD238A standard. It offers multiple advantages over previous releases of HBM technology in terms of speed, latency, and computational capabilities. The HBM3 technology implements RAS architecture for reducing memory error rates.

Second Generation of HBM implements 2.4 Gb/s/pin with 307-346 GB/s. Further, HBM2E implements 5.0 Gb/s/pin with 640 Gb/s, and third Generation of HBM implements 8.0 Gb/s/pin with 1024 GB/s.

A table describing about comparison of HBM2, HBM2E, And HBM3:

We have tried collecting all available information on the internet related to the HBM3 memory system. The blog includes documents of different versions of standards, related products, and IEEE Papers from manufacturers.

Different HBM standards released by JEDEC

Multiple version of the HBM memory system and their links are:

HBM1: JESD235: (Oct 2013): https://www.jedec.org/sites/default/files/docs/JESD235.pdf 
HBM2: JESD235A: (Nov 2015): https://web.archive.org/web/20220514151205/https://composter.com.ua/documents/JESD235A.pdf
HBM2E: JESD235B: (Nov 2018): not available
HBM2 Update: JESD235C: (Jan 2020): not available
HBM1, HBM2: JESD235D: : (Feb 2021): https://www.jedec.org/sites/default/files/docs/JESD235D.pdf
HBM3: JESD238: (Jan 2022): not available
HBM3 update: JESD238A: (Jan 2023): https://www.jedec.org/sites/default/files/docs/JESD238A.pdf

HBM1: 

JEDEC released the first version of the HBM standard, named HBM1 (JESD235 standard), in October 2013, and its link is below:

https://www.jedec.org/sites/default/files/docs/JESD235.pdf

HBM2:

JEDEC released the second version of the HBM standard, named HBM2 (JESD235A standard), in November 2015, and its link is below:

https://web.archive.org/web/20220514151205/https://composter.com.ua/documents/JESD235A.pdf

Further, JEDEC released the third version of the HBM standard named HBM2E (JESD235B standard) in November 2018 and HBM2 Updation (JESD235C) in January 2020. The link is not available on the internet.

HBM3:

JEDEC released a new version of the HBM standard named HBM3 (JESD238A standard) on Jan 2023, and its link is

https://www.jedec.org/sites/default/files/docs/JESD238A.pdf

Multiple new Features introduced in HBM3 are:

New features introduced in HBM3 for increasing memory speed and reducing memory latency are:

  1. On-Die DRAM ECC Operation
  2. Automated on-die error scrubbing mechanism (Error Check and Scrub (ECS) operation)
  3. MBIST enhanced memory built-in self-test (MBIST)
  4. WDQS Interval Oscillator
  5. Duty Cycle Adjuster (DCA) | Duty Cycle Monitor (DCM)
  6. Self-Repair Mechanism


Different IEEE Papers from other manufacturers are available. Manufacturers are working on HBM3 memory standard JEDEC JESD238A for various memory operations. They are implementing a new mechanism introduced in the HBM3 standard.

Samsung and SK Hynix are significant manufacturers of HBM3 and have revealed many research papers stating or indicating their implementation of different features of HBM3. The paper describes how various implemented technical features are introduced in the HBM3 memory system.

Products implementing HBM3 technology:

Products implementing HBM3 technology

SAMSUNG HBM3 ICEBOLT:

The memory system stacks 12 stacks of DRAM memory systems for AI operations. It provides processing speeds up to 6.4Gbps and bandwidth that reaches 819GB/s.

SAMSUNG HBM3 ICEBOLT
Fig 1. Samsung HBM3 ICEBOLT variants

Link to this product: https://semiconductor.samsung.com/dram/hbm/hbm3-icebolt/

SKHYNIX HBM3 memory system:

SKhynix announces 12 layers of HBM3 with 24 GB memory capacity

Fig 2. SK Hynix HBM3 24 GB memory system

Link to this product: https://news.skhynix.com/sk-hynix-develops-industrys-first-12-layer-hbm3/

Nvidia Hopper H100 GPU implementing HBM3 memory system:

Nvidia Hopper H100 GPU implementing HBM3 memory system
Fig 3. Nvidia Hopper H100 GPU implementing HBM3 memory system

IEEE Papers from different Manufacturers exploring HBM3 technology

IEEE papers and their links from Samsung, SK Hynix, and Nvidia are mentioned. These papers are written authors from Samsung, SK Hynix, and Nvidia. The authors are exploring different technological aspects of the HBM3 memory system. The IEEE paper shows the architecture of the HBM memory system and various features:

Samsung IEEE paper related to HBM3:

Samsung has been working on HBM3 technology and has already released multiple products about it.

IEEE Paper1:

Title: A 4nm 1.15TB/s HBM3 Interface with Resistor-Tuned Offset-Calibration and In-Situ Margin-Detection
DOI10.1109/ISSCC42615.2023.10067736
Link: https://ieeexplore.ieee.org/document/10067736

IEEE Paper2:

Title: A 16 GB 1024 GB/s HBM3 DRAM with On-Die Error Control Scheme for Enhanced RAS Features
DOI10.1109/VLSITechnologyandCir46769.2022.9830391
Link: https://ieeexplore.ieee.org/document/9830391

IEEE Paper3:

Title: A 16 GB 1024 GB/s HBM3 DRAM With Source-Synchronized Bus Design and On-Die Error Control Scheme for Enhanced RAS Features
DOI10.1109/JSSC.2022.3232096
Link: https://ieeexplore.ieee.org/document/10005600

Samsung HBM3 Architecture
Fig 4. Samsung HBM3 architecture

Data-bus architecture of HBM2E and HBM3
Fig 5. Data-bus architecture of HBM2E and HBM3

SK Hynix IEEE paper related to HBM3:

SK Hynix has also published 2 IEEE papers describing the HBM3 memory technological aspect.

IEEE Paper 1 and IEEE Paper 2 of SK Hynix:

IEEE Paper1:

Title: A 192-Gb 12-High 896-GB/s HBM3 DRAM With a TSV Auto-Calibration Scheme and Machine-Learning-Based Layout Optimization|
DOI: 10.1109/ISSCC42614.2022.9731562
Link: https://ieeexplore.ieee.org/document/9731562

IEEE Paper2:

Title: A 192-Gb 12-High 896-GB/s HBM3 DRAM With a TSV Auto-Calibration Scheme and Machine-Learning-Based Layout Optimization
DOI: 10.23919/VLSIC.2019.8778082
Link: https://ieeexplore.ieee.org/document/8778082/

SK Hynix architecture of HBM3 memory system
Fig 6. SK Hynix architecture of HBM3 memory system.

Nvidia IEEE paper related to HBM3:

Nvidia has also published 1 IEEE paper about the HBM3 memory system. The paper describes that Hopper H100 GPU is implementing five HBM memory systems with a total memory bandwidth of over 3TB/s.

IEEE Paper1:

Title: NVIDIA Hopper H100 GPU: Scaling Performance
DOI10.1109/ISSCC42614.2022.9731562
Link: https://ieeexplore.ieee.org/abstract/document/10070122

Nvidia Hopper H100 implementing HBM3 memory system
Fig 7. Nvidia Hopper H100 implementing HBM3 memory system.

TSMC IEEE paper related to HBM3:

TSMC has also published 1 IEEE paper pertaining to the HBM3 memory system. The paper implements integrated de-cap capacitors for suppressing power domain noise and for enhancing the HBM3 signal integrity at a high data rate.

IEEE Paper1:

Title: Heterogeneous and Chiplet Integration Using Organic Interposer (CoWoS-R)
DOI10.1109/ISSCC42614.2022.9731562
Link: https://ieeexplore.ieee.org/document/10019517/

HBM and Chiplet side of a system
Fig 8. HBM and Chiplet side of a system

Categories
Computer Science

DDR5’s Secret Weapon: On-Die Termination (ODT) for Noise Reduction and Power Efficiency

Enhancing data reliability and performance: Exploring On-die termination (ODT) in DDR5 memory

Signal integrity is more important as data is delivered at faster speeds in DDR5 memory. When there is an imbalance between the characteristic impedance of the transmission line and the impedance of the connected devices, signal reflections may happen. DDR5 (Double Data Rate 5) memory modules and other high-speed digital systems use the on-die termination (ODT) technology to lessen signal reflections and enhance signal integrity.

By placing a termination resistor that matches the transmission line’s impedance right on the memory chip, on-die termination minimizes the possibility of signal reflections. Therefore, ODT is a crucial component for high-speed DDR5 memory systems since it aids in enhancing signal quality, decreasing signal ringing, and eventually allowing for higher data transfer speeds with less signal deterioration.  

To other circuity like RCV: DQ, DS, DM, TDQS

[Source: DDR5 Standard [JEDEC JESD79-5B_v1.20] Page 346 of 502]

P.S. You can refer to DDR5 Standard [JEDEC JESD79-5B_v1.20]: https://www.jedec.org/sites/default/files/docs/JESD79-5B_v1-2.pdf for further studies.     

With on-die termination (ODT), the termination resistor for transmission line impedance matching is housed inside a semiconductor chip as opposed to a printed circuit board (PCB). This termination resistor can be dynamically enabled or disabled depending on the settings of the memory controller and the particular needs of the memory bus.   

Types of On-Die Termination (ODT) in DDR5

There are two primary ODT implementation types in DDR5 memory:

ODT in parallel (PODT)

The conventional ODT technique used in earlier DDR memory generations is called Parallel On-Die Termination. The data lines on the memory chip are connected in parallel with a fixed termination resistor in PODT. Regardless of whether the ODT is activated or disabled, this resistor offers a constant impedance to the data lines. On a memory module, the termination value is commonly selected to match the characteristic impedance of the transmission lines.

Dynamic On-Die Termination (DODT)

It is a more sophisticated ODT technology that was introduced with DDR5 memory. When using DODT, the termination impedance can be changed dynamically, in contrast to PODT. According to the settings of the memory controller and the precise data transfer requirements at any given time, the termination resistor can be changed or turned on or off. With the aid of this dynamic management, signal integrity can be improved for a range of data rates and load situations.

PODT v. DODT

Parallel ODT:

  • The termination impedance in parallel ODT is constant and does not fluctuate.
  • In order to change between high and low termination impedances, a mode register set instruction is necessary.
  • The termination resistor is positioned on the motherboard in this example of the termination method.

Dynamic ODT:

  • The DRAM may flip between high and low termination impedance thanks to dynamic ODT without requiring a mode register set instruction.
  • It gives systems more freedom to choose the best termination values under various loading scenarios.
  • Without executing a mode register set instruction, it enables the DRAM to alternate between high and low termination impedance.
  • It simplifies and lowers the cost of the system design by reducing the amount of complicated wire and resistor parts on the motherboard.

In conclusion, the primary distinction between parallel ODT and dynamic ODT is that the former has a fixed termination impedance while the latter enables dynamic impedance switching without the requirement of a mode register set instruction. Increased flexibility and optimization for various loading circumstances are provided by dynamic ODT.

Key features of ODT in DDR5

Certainly! On-Die-Termination (ODT), which plays a critical part in guaranteeing dependable and effective high-speed data transmission, is particularly significant in DDR5 memory. ODT addresses several significant issues that develop as data transmission rates climb in contemporary memory systems. The following are the primary implications of ODT in DDR5:

Signal Reflection Reduction

Due to the nature of high-speed digital transmissions, signal reflections and impedance mismatches occur when data signals are carried across the memory bus. These reflections may deteriorate the quality of the delivered data and distort the signal. To lessen signal reflections and minimize data errors, ODT offers termination resistors that are directly attached to the memory chips and match the characteristic impedance of the transmission lines.

Data Reliability

Due to DDR5’s faster data transfer speeds, there is also a greater chance of data mistakes and corruption. Data distortions and signal ringing are reduced by proper termination utilizing ODT, resulting in more dependable data transfer and a lower probability of memory-related mistakes. ODT improves memory performance by allowing memory modules to run at their full specified speeds by reducing signal reflections and distortions.

Noise reduction

ODT aids in the memory system’s ability to filter out noise and electromagnetic interference (EMI). For signal quality to be maintained and to prevent data corruption or system instability, noise reduction is essential.

Power Efficiency

The Dynamic On-Die Termination (DODT) feature of DDR5 memory enables dynamic management of the termination impedance. DODT optimizes power usage by changing the termination parameters in accordance with the demands of the data transfer. The amount of unnecessary power dissipation is reduced, making the memory system more power-efficient.

Flexibility  

DODT provides more flexibility in memory operations because it is a dynamic implementation of ODT. Memory controllers offer superior adaptability to changing circumstances by adjusting termination settings for various memory configurations, data rates, and system loads.

Intellectual property trends for ODT

ODT in DDR5 is witnessing rapid growth in patent filing trends across the globe. Over the past few years, the number of patent applications almost getting doubled every two years.   

MICRON is a dominant player in the market with ~426 patents. So far, it has 2 times more patents than Intel. AMD is the third-largest patent holder in the domain.

Other key players who have filed for patents in DDR5 technology with ODT are SK Hynix, NVDIA, Samsung, IBM, Qualcomm and IBM.

Other key players who have filed for patents in DDR5 technology with ODT are SK Hynix, NVDIA, Samsung, IBM, Qualcomm and IBM

[Source: https://www.lens.org/lens/search/patent/list?q=on-die%20termination%20on%20DDR5%20memory]

Following are the trends of publication and their legal status over time:

[Source: https://www.lens.org/lens/search/patent/list?q=on-die%20termination%20on%20DDR5%20memory

These Top 10 companies own around 54% of total patents related to HBM. The below diagram shows these companies have built strong IPMoats in US jurisdiction, followed by China, European, Korea, and Germany jurisdiction.

[Source: https://www.lens.org/lens/search/patent/list?q=on-die%20termination%20on%20DDR5%20memory]

Conclusion

ODT is becoming more and more important as memory technologies develop. Strong signal integrity and effective data transmission become more crucial with each new memory generation and higher data rates. The use of ODT in DDR5 helps memory systems be prepared for future increases in performance and data transfer speeds. In conclusion, ODT helps to provide a stable and dependable memory system that can support the needs of contemporary computer applications by reducing signal reflections and noise.

Categories
Computer Science

Recommendation Systems: Navigating the Digital Deluge for Personalized Experiences

In today’s digital age, we are constantly blasted with an overwhelming amount of information, products, and services. Recommendation systems have emerged as an invaluable tool to help us navigate through this vast sea of choices. Whether we are browsing an e-commerce website, streaming our favorite shows, or discovering new music, recommendation systems play a pivotal role in enhancing our online experiences. In this blog post, we will explore what recommendation systems are, how they work, and the underlying algorithms that power them.

What are Recommendation Systems?

A Recommender system predicts whether a particular user would prefer an item or not based on the user’s profile and user’s information. These systems aim to overcome information overload and provide personalized recommendations to a particular user.

The term recommender system provides personalized suggestions as a result and it affects the user in an individualized way to Favourable items from the large number of opinions. Recommendation systems are becoming increasingly important in today’s extremely busy world. People are always short on time with the myriad tasks they need to accomplish in the limited 24 hours. Therefore, the recommendation systems are important as they help them make the right choices, without having to expend their cognitive resources.

Understanding the Recommendation Algorithms:

Recommendation Algorithms: Recommendation algorithms are at the core of any recommendation system. There are several types of algorithms used, including.

  • Content-Based Filtering: Content-based filtering recommends items similar to those a user has liked or interacted with in the past. It analyses item attributes and user profiles to identify patterns and make recommendations based on similarity.
  • Collaborative Filtering: Collaborative filtering utilizes user behavior and preferences to recommend items. It looks for patterns and relationships between users with similar tastes and suggests items based on what similar users have liked or purchased.
  • Hybrid Approaches: Hybrid approaches combine multiple algorithms to leverage the strengths of both content-based and collaborative filtering. By using hybrid models, recommendation systems can provide more accurate and diverse recommendations.
  • Matrix Factorization: Matrix factorization techniques, such as Singular Value Decomposition (SVD) and Non-Negative Matrix Factorization (NMF), decompose the user-item interaction matrix into lower-dimensional matrices. These techniques capture latent factors or features that represent user preferences and item characteristics. By reconstructing the original matrix, the algorithm can predict the missing ratings or recommend items based on the inferred latent factors.
  • Association Rules: Association rule-based algorithms discover relationships and associations between items based on the co-occurrence of items in user transactions. The algorithm identifies frequently occurring item sets and generates recommendations based on these associations. For example, if many users who purchase diapers also buy baby food, the algorithm may suggest baby food to users who have bought diapers.

Conclusion:

Recommendation systems have revolutionized the way we discover and engage with content, products, and services online. By harnessing the power of data and advanced algorithms, these systems provide tailored recommendations, enhancing user experiences and driving engagement. As technology advances, recommendation systems will continue to evolve, becoming even more accurate, personalized, and indispensable in our digital lives.

Remember, the next time you stumble upon a perfectly curated playlist or discover a book that seems tailor-made for you, you have recommendation systems.